6d45770d98
Move command registry from components/command/ into components/core/. New modules: mod_canbus, mod_honeypot, mod_fallback, mod_redteam, mod_ota. Replace mod_proxy with tun_core (multiplexed SOCKS5 tunnel). Kconfig extended with per-module settings and async worker config.
816 lines
24 KiB
C
816 lines
24 KiB
C
/*
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* canbus_driver.c
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* MCP2515 CAN 2.0B controller driver via ESP-IDF SPI master.
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*
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* Architecture:
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* GPIO ISR (INT pin, active low) → binary semaphore → RX task → callback
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* TX: direct SPI writes to TX buffer 0, poll for completion.
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*/
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#include "sdkconfig.h"
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#ifdef CONFIG_MODULE_CANBUS
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#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "driver/spi_master.h"
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#include "driver/gpio.h"
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#include "esp_timer.h"
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#include "esp_log.h"
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#include "canbus_driver.h"
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#define TAG "CAN_DRV"
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/* ============================================================
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* MCP2515 SPI Instructions
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* ============================================================ */
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#define MCP_RESET 0xC0
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#define MCP_READ 0x03
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#define MCP_WRITE 0x02
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#define MCP_BIT_MODIFY 0x05
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#define MCP_READ_STATUS 0xA0
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#define MCP_RX_STATUS 0xB0
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#define MCP_READ_RX0 0x90 /* Read RX buffer 0 starting at SIDH */
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#define MCP_READ_RX1 0x94 /* Read RX buffer 1 starting at SIDH */
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#define MCP_LOAD_TX0 0x40 /* Load TX buffer 0 starting at SIDH */
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#define MCP_RTS_TX0 0x81 /* Request-To-Send TX buffer 0 */
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/* ============================================================
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* MCP2515 Registers
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* ============================================================ */
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#define MCP_CANCTRL 0x0F
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#define MCP_CANSTAT 0x0E
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#define MCP_CNF1 0x2A
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#define MCP_CNF2 0x29
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#define MCP_CNF3 0x28
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#define MCP_CANINTE 0x2B
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#define MCP_CANINTF 0x2C
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#define MCP_EFLG 0x2D
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#define MCP_TEC 0x1C
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#define MCP_REC 0x1D
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/* RXB0CTRL / RXB1CTRL */
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#define MCP_RXB0CTRL 0x60
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#define MCP_RXB1CTRL 0x70
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/* Filter/mask registers */
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#define MCP_RXF0SIDH 0x00
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#define MCP_RXF1SIDH 0x04
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#define MCP_RXF2SIDH 0x08
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#define MCP_RXF3SIDH 0x10
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#define MCP_RXF4SIDH 0x14
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#define MCP_RXF5SIDH 0x18
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#define MCP_RXM0SIDH 0x20
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#define MCP_RXM1SIDH 0x24
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/* TXB0 registers */
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#define MCP_TXB0CTRL 0x30
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#define MCP_TXB0SIDH 0x31
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/* CANCTRL mode bits */
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#define MCP_MODE_NORMAL 0x00
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#define MCP_MODE_LISTEN 0x60
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#define MCP_MODE_LOOPBACK 0x40
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#define MCP_MODE_CONFIG 0x80
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/* CANINTF bits */
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#define MCP_RX0IF 0x01
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#define MCP_RX1IF 0x02
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#define MCP_TX0IF 0x04
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#define MCP_TX1IF 0x08
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#define MCP_TX2IF 0x10
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#define MCP_ERRIF 0x20
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#define MCP_WAKIF 0x40
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#define MCP_MERRF 0x80
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/* CANINTE bits */
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#define MCP_RX0IE 0x01
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#define MCP_RX1IE 0x02
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#define MCP_ERRIE 0x20
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/* EFLG bits */
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#define MCP_EFLG_RX0OVR 0x40
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#define MCP_EFLG_RX1OVR 0x80
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#define MCP_EFLG_TXBO 0x20
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#define MCP_EFLG_RXEP 0x10
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#define MCP_EFLG_TXEP 0x08
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/* ============================================================
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* Bit Timing Tables
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* ============================================================ */
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typedef struct {
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int bitrate;
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uint8_t cnf1, cnf2, cnf3;
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} can_timing_t;
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/* 16 MHz oscillator — TQ = 2/Fosc = 125ns */
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static const can_timing_t s_timing_16mhz[] = {
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{ 1000000, 0x00, 0xCA, 0x01 }, /* 1 Mbps: SJW=1, BRP=0, 8 TQ */
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{ 500000, 0x00, 0xF0, 0x86 }, /* 500 kbps: SJW=1, BRP=0, 16 TQ */
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{ 250000, 0x01, 0xF0, 0x86 }, /* 250 kbps: SJW=1, BRP=1, 16 TQ */
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{ 125000, 0x03, 0xF0, 0x86 }, /* 125 kbps: SJW=1, BRP=3, 16 TQ */
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{ 100000, 0x04, 0xF0, 0x86 }, /* 100 kbps: SJW=1, BRP=4, 16 TQ */
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{ 0, 0, 0, 0 }
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};
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/* 8 MHz oscillator — TQ = 2/Fosc = 250ns */
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static const can_timing_t s_timing_8mhz[] = {
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{ 500000, 0x00, 0x90, 0x02 }, /* 500 kbps: SJW=1, BRP=0, 8 TQ */
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{ 250000, 0x00, 0xF0, 0x86 }, /* 250 kbps: SJW=1, BRP=0, 16 TQ */
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{ 125000, 0x01, 0xF0, 0x86 }, /* 125 kbps: SJW=1, BRP=1, 16 TQ */
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{ 100000, 0x03, 0xAC, 0x03 }, /* 100 kbps: SJW=1, BRP=3, 10 TQ */
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{ 0, 0, 0, 0 }
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};
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/* ============================================================
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* Driver State
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* ============================================================ */
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static spi_device_handle_t s_spi = NULL;
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static TaskHandle_t s_rx_task = NULL;
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static SemaphoreHandle_t s_int_sem = NULL;
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static SemaphoreHandle_t s_tx_mutex = NULL;
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static volatile bool s_running = false;
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static can_rx_callback_t s_rx_cb = NULL;
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static void *s_rx_ctx = NULL;
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/* Counters */
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static uint32_t s_rx_count = 0;
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static uint32_t s_tx_count = 0;
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static uint32_t s_bus_errors = 0;
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static uint32_t s_rx_overflow = 0;
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static bool s_bus_off = false;
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static bool s_err_passive = false;
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/* ============================================================
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* SPI Low-Level Helpers
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* ============================================================ */
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static uint8_t mcp_read_reg(uint8_t addr)
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{
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uint8_t tx[3] = { MCP_READ, addr, 0x00 };
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uint8_t rx[3] = { 0 };
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spi_transaction_t t = {
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.length = 24,
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.tx_buffer = tx,
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.rx_buffer = rx,
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};
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spi_device_transmit(s_spi, &t);
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return rx[2];
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}
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static void mcp_write_reg(uint8_t addr, uint8_t val)
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{
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uint8_t tx[3] = { MCP_WRITE, addr, val };
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spi_transaction_t t = {
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.length = 24,
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.tx_buffer = tx,
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};
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spi_device_transmit(s_spi, &t);
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}
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static void mcp_modify_reg(uint8_t addr, uint8_t mask, uint8_t val)
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{
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uint8_t tx[4] = { MCP_BIT_MODIFY, addr, mask, val };
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spi_transaction_t t = {
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.length = 32,
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.tx_buffer = tx,
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};
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spi_device_transmit(s_spi, &t);
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}
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static void mcp_reset(void)
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{
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uint8_t tx[1] = { MCP_RESET };
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spi_transaction_t t = {
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.length = 8,
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.tx_buffer = tx,
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};
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spi_device_transmit(s_spi, &t);
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vTaskDelay(pdMS_TO_TICKS(10)); /* MCP2515 needs time after reset */
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}
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static void mcp_set_mode(uint8_t mode)
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{
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mcp_modify_reg(MCP_CANCTRL, 0xE0, mode);
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/* Wait for mode change confirmation */
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for (int i = 0; i < 50; i++) {
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uint8_t stat = mcp_read_reg(MCP_CANSTAT);
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if ((stat & 0xE0) == mode) return;
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vTaskDelay(pdMS_TO_TICKS(1));
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}
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ESP_LOGW(TAG, "Mode change to 0x%02X timeout", mode);
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}
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/* Read a complete frame from RX buffer (0 or 1) */
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static void mcp_read_rx_buffer(int buf, can_frame_t *frame)
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{
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/* Use READ_RX instruction for auto-clear of interrupt flag */
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uint8_t cmd = (buf == 0) ? MCP_READ_RX0 : MCP_READ_RX1;
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/* Read: cmd + SIDH + SIDL + EID8 + EID0 + DLC + 8 data = 14 bytes */
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uint8_t tx[14] = { 0 };
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uint8_t rx[14] = { 0 };
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tx[0] = cmd;
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spi_transaction_t t = {
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.length = 14 * 8,
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.tx_buffer = tx,
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.rx_buffer = rx,
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};
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spi_device_transmit(s_spi, &t);
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/* Parse — offsets relative to rx[1] (SIDH is byte 1) */
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uint8_t sidh = rx[1];
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uint8_t sidl = rx[2];
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uint8_t eid8 = rx[3];
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uint8_t eid0 = rx[4];
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uint8_t dlc = rx[5];
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frame->extended = (sidl & 0x08) != 0;
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frame->rtr = false;
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if (frame->extended) {
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frame->id = ((uint32_t)sidh << 21)
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| ((uint32_t)(sidl & 0xE0) << 13)
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| ((uint32_t)(sidl & 0x03) << 16)
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| ((uint32_t)eid8 << 8)
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| (uint32_t)eid0;
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frame->rtr = (dlc & 0x40) != 0;
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} else {
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frame->id = ((uint32_t)sidh << 3) | ((uint32_t)(sidl >> 5) & 0x07);
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frame->rtr = (sidl & 0x10) != 0;
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}
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frame->dlc = dlc & 0x0F;
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if (frame->dlc > 8) frame->dlc = 8;
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memcpy(frame->data, &rx[6], 8);
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frame->timestamp_us = 0; /* Caller sets timestamp */
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}
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/* Write a frame to TX buffer 0 and request send */
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static bool mcp_write_tx_buffer(const can_frame_t *frame)
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{
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/* Check if TX buffer 0 is free */
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uint8_t ctrl = mcp_read_reg(MCP_TXB0CTRL);
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if (ctrl & 0x08) {
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/* TXREQ still set — previous TX pending */
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return false;
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}
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/* Build TX buffer content: SIDH + SIDL + EID8 + EID0 + DLC + data */
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uint8_t tx[14] = { 0 };
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tx[0] = MCP_LOAD_TX0;
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if (frame->extended) {
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tx[1] = (uint8_t)(frame->id >> 21); /* SIDH */
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tx[2] = (uint8_t)((frame->id >> 13) & 0xE0) /* SIDL high bits */
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| 0x08 /* EXIDE = 1 */
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| (uint8_t)((frame->id >> 16) & 0x03); /* SIDL low bits */
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tx[3] = (uint8_t)(frame->id >> 8); /* EID8 */
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tx[4] = (uint8_t)(frame->id); /* EID0 */
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tx[5] = frame->dlc | (frame->rtr ? 0x40 : 0x00); /* DLC + RTR */
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} else {
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tx[1] = (uint8_t)(frame->id >> 3); /* SIDH */
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tx[2] = (uint8_t)((frame->id & 0x07) << 5) /* SIDL */
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| (frame->rtr ? 0x10 : 0x00);
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tx[3] = 0;
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tx[4] = 0;
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tx[5] = frame->dlc;
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}
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memcpy(&tx[6], frame->data, 8);
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spi_transaction_t t = {
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.length = 14 * 8,
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.tx_buffer = tx,
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};
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spi_device_transmit(s_spi, &t);
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/* Request to send */
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uint8_t rts = MCP_RTS_TX0;
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spi_transaction_t rts_t = {
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.length = 8,
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.tx_buffer = &rts,
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};
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spi_device_transmit(s_spi, &rts_t);
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return true;
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}
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/* ============================================================
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* GPIO ISR — INT pin (active low)
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* ============================================================ */
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static void IRAM_ATTR gpio_isr_handler(void *arg)
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{
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BaseType_t woken = pdFALSE;
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xSemaphoreGiveFromISR(s_int_sem, &woken);
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if (woken) portYIELD_FROM_ISR();
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}
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/* ============================================================
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* RX Task
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* ============================================================ */
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static void rx_task(void *arg)
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{
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ESP_LOGI(TAG, "RX task started");
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while (s_running) {
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/* Wait for interrupt or timeout (poll every 100ms as fallback) */
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if (xSemaphoreTake(s_int_sem, pdMS_TO_TICKS(100)) != pdTRUE) {
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continue;
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}
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/* Read interrupt flags */
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uint8_t intf = mcp_read_reg(MCP_CANINTF);
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/* RX buffer 0 full */
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if (intf & MCP_RX0IF) {
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can_frame_t frame;
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mcp_read_rx_buffer(0, &frame); /* READ_RX auto-clears RX0IF */
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frame.timestamp_us = esp_timer_get_time();
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s_rx_count++;
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if (s_rx_cb) s_rx_cb(&frame, s_rx_ctx);
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}
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/* RX buffer 1 full */
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if (intf & MCP_RX1IF) {
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can_frame_t frame;
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mcp_read_rx_buffer(1, &frame); /* READ_RX auto-clears RX1IF */
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frame.timestamp_us = esp_timer_get_time();
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s_rx_count++;
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if (s_rx_cb) s_rx_cb(&frame, s_rx_ctx);
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}
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/* Error interrupt */
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if (intf & MCP_ERRIF) {
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uint8_t eflg = mcp_read_reg(MCP_EFLG);
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s_bus_errors++;
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if (eflg & MCP_EFLG_TXBO) {
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s_bus_off = true;
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ESP_LOGW(TAG, "Bus-off detected");
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}
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if (eflg & (MCP_EFLG_RXEP | MCP_EFLG_TXEP)) {
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s_err_passive = true;
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}
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if (eflg & (MCP_EFLG_RX0OVR | MCP_EFLG_RX1OVR)) {
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s_rx_overflow++;
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}
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/* Clear error flags */
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mcp_modify_reg(MCP_EFLG, 0xFF, 0x00);
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mcp_modify_reg(MCP_CANINTF, MCP_ERRIF, 0x00);
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}
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/* TX complete — clear flags */
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if (intf & (MCP_TX0IF | MCP_TX1IF | MCP_TX2IF)) {
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mcp_modify_reg(MCP_CANINTF, MCP_TX0IF | MCP_TX1IF | MCP_TX2IF, 0x00);
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}
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}
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ESP_LOGI(TAG, "RX task stopped");
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s_rx_task = NULL;
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vTaskDelete(NULL);
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}
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/* ============================================================
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* Public API — Lifecycle
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* ============================================================ */
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bool can_driver_init(int bitrate, uint8_t osc_mhz)
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{
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if (s_spi) {
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ESP_LOGW(TAG, "Already initialized");
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return false;
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}
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/* Select timing table */
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const can_timing_t *table = NULL;
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if (osc_mhz == 16) {
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table = s_timing_16mhz;
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} else if (osc_mhz == 8) {
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table = s_timing_8mhz;
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} else {
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ESP_LOGE(TAG, "Unsupported oscillator: %u MHz", osc_mhz);
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return false;
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}
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/* Find matching bitrate */
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const can_timing_t *timing = NULL;
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for (int i = 0; table[i].bitrate != 0; i++) {
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if (table[i].bitrate == bitrate) {
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timing = &table[i];
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break;
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}
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}
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if (!timing) {
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ESP_LOGE(TAG, "Unsupported bitrate %d for %u MHz osc", bitrate, osc_mhz);
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return false;
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}
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/* Init SPI bus */
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spi_bus_config_t bus_cfg = {
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.mosi_io_num = CONFIG_CANBUS_PIN_MOSI,
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.miso_io_num = CONFIG_CANBUS_PIN_MISO,
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.sclk_io_num = CONFIG_CANBUS_PIN_SCK,
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.quadwp_io_num = -1,
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.quadhd_io_num = -1,
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.max_transfer_sz = 32,
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};
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esp_err_t ret = spi_bus_initialize(CONFIG_CANBUS_SPI_HOST, &bus_cfg, SPI_DMA_DISABLED);
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if (ret != ESP_OK) {
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ESP_LOGE(TAG, "SPI bus init failed: %s", esp_err_to_name(ret));
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return false;
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}
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/* Add MCP2515 as SPI device */
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spi_device_interface_config_t dev_cfg = {
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.mode = 0, /* SPI mode 0 (CPOL=0, CPHA=0) */
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.clock_speed_hz = CONFIG_CANBUS_SPI_CLOCK_HZ,
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.spics_io_num = CONFIG_CANBUS_PIN_CS,
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.queue_size = 4,
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};
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ret = spi_bus_add_device(CONFIG_CANBUS_SPI_HOST, &dev_cfg, &s_spi);
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if (ret != ESP_OK) {
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ESP_LOGE(TAG, "SPI device add failed: %s", esp_err_to_name(ret));
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spi_bus_free(CONFIG_CANBUS_SPI_HOST);
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return false;
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}
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/* Reset MCP2515 (enters CONFIG mode automatically) */
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mcp_reset();
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/* Verify we can read CANSTAT — should be in CONFIG mode (0x80) */
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uint8_t stat = mcp_read_reg(MCP_CANSTAT);
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if ((stat & 0xE0) != MCP_MODE_CONFIG) {
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ESP_LOGE(TAG, "MCP2515 not responding (CANSTAT=0x%02X)", stat);
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spi_bus_remove_device(s_spi);
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spi_bus_free(CONFIG_CANBUS_SPI_HOST);
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s_spi = NULL;
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return false;
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}
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ESP_LOGI(TAG, "MCP2515 detected (CANSTAT=0x%02X)", stat);
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/* Set bit timing */
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mcp_write_reg(MCP_CNF1, timing->cnf1);
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mcp_write_reg(MCP_CNF2, timing->cnf2);
|
|
mcp_write_reg(MCP_CNF3, timing->cnf3);
|
|
|
|
/* Enable interrupts: RX0, RX1, Error */
|
|
mcp_write_reg(MCP_CANINTE, MCP_RX0IE | MCP_RX1IE | MCP_ERRIE);
|
|
|
|
/* Clear all interrupt flags */
|
|
mcp_write_reg(MCP_CANINTF, 0x00);
|
|
|
|
/* RXB0CTRL: rollover to RXB1 if RXB0 full, receive all valid messages */
|
|
mcp_write_reg(MCP_RXB0CTRL, 0x64); /* BUKT=1, RXM=11 (turn mask/filter off) */
|
|
mcp_write_reg(MCP_RXB1CTRL, 0x60); /* RXM=11 (turn mask/filter off) */
|
|
|
|
/* Create semaphores */
|
|
s_int_sem = xSemaphoreCreateBinary();
|
|
s_tx_mutex = xSemaphoreCreateMutex();
|
|
|
|
/* Reset counters */
|
|
s_rx_count = 0;
|
|
s_tx_count = 0;
|
|
s_bus_errors = 0;
|
|
s_rx_overflow = 0;
|
|
s_bus_off = false;
|
|
s_err_passive = false;
|
|
|
|
/* Configure INT pin as input with pull-up, falling edge interrupt */
|
|
gpio_config_t io_cfg = {
|
|
.pin_bit_mask = (1ULL << CONFIG_CANBUS_PIN_INT),
|
|
.mode = GPIO_MODE_INPUT,
|
|
.pull_up_en = GPIO_PULLUP_ENABLE,
|
|
.pull_down_en = GPIO_PULLDOWN_DISABLE,
|
|
.intr_type = GPIO_INTR_NEGEDGE,
|
|
};
|
|
gpio_config(&io_cfg);
|
|
gpio_install_isr_service(0);
|
|
gpio_isr_handler_add(CONFIG_CANBUS_PIN_INT, gpio_isr_handler, NULL);
|
|
|
|
ESP_LOGI(TAG, "Initialized: %d bps, %u MHz osc, SPI@%d Hz",
|
|
bitrate, osc_mhz, CONFIG_CANBUS_SPI_CLOCK_HZ);
|
|
return true;
|
|
}
|
|
|
|
bool can_driver_start(can_mode_t mode)
|
|
{
|
|
if (!s_spi) {
|
|
ESP_LOGE(TAG, "Not initialized");
|
|
return false;
|
|
}
|
|
if (s_running) {
|
|
ESP_LOGW(TAG, "Already running");
|
|
return false;
|
|
}
|
|
|
|
/* Map mode enum to MCP2515 mode register value */
|
|
uint8_t mcp_mode;
|
|
const char *mode_str;
|
|
switch (mode) {
|
|
case CAN_MODE_LISTEN_ONLY:
|
|
mcp_mode = MCP_MODE_LISTEN;
|
|
mode_str = "listen-only";
|
|
break;
|
|
case CAN_MODE_LOOPBACK:
|
|
mcp_mode = MCP_MODE_LOOPBACK;
|
|
mode_str = "loopback";
|
|
break;
|
|
default:
|
|
mcp_mode = MCP_MODE_NORMAL;
|
|
mode_str = "normal";
|
|
break;
|
|
}
|
|
|
|
/* Set operational mode */
|
|
mcp_set_mode(mcp_mode);
|
|
|
|
/* Verify mode */
|
|
uint8_t stat = mcp_read_reg(MCP_CANSTAT);
|
|
if ((stat & 0xE0) != mcp_mode) {
|
|
ESP_LOGE(TAG, "Failed to enter %s mode (CANSTAT=0x%02X)", mode_str, stat);
|
|
return false;
|
|
}
|
|
|
|
s_running = true;
|
|
|
|
/* Start RX task on Core 1, priority 5 (above normal) */
|
|
BaseType_t ret = xTaskCreatePinnedToCore(
|
|
rx_task, "can_rx", 4096, NULL, 5, &s_rx_task, 1
|
|
);
|
|
if (ret != pdPASS) {
|
|
ESP_LOGE(TAG, "Failed to create RX task");
|
|
s_running = false;
|
|
mcp_set_mode(MCP_MODE_CONFIG);
|
|
return false;
|
|
}
|
|
|
|
ESP_LOGI(TAG, "Started in %s mode", mode_str);
|
|
return true;
|
|
}
|
|
|
|
void can_driver_stop(void)
|
|
{
|
|
if (!s_running) return;
|
|
|
|
s_running = false;
|
|
|
|
/* Give semaphore to wake RX task so it exits */
|
|
if (s_int_sem) xSemaphoreGive(s_int_sem);
|
|
|
|
/* Wait for RX task to die */
|
|
for (int i = 0; i < 20 && s_rx_task != NULL; i++) {
|
|
vTaskDelay(pdMS_TO_TICKS(50));
|
|
}
|
|
|
|
/* Put MCP2515 back to CONFIG mode */
|
|
if (s_spi) {
|
|
mcp_set_mode(MCP_MODE_CONFIG);
|
|
}
|
|
|
|
ESP_LOGI(TAG, "Stopped");
|
|
}
|
|
|
|
void can_driver_deinit(void)
|
|
{
|
|
can_driver_stop();
|
|
|
|
/* Remove ISR */
|
|
gpio_isr_handler_remove(CONFIG_CANBUS_PIN_INT);
|
|
|
|
/* Free SPI */
|
|
if (s_spi) {
|
|
spi_bus_remove_device(s_spi);
|
|
spi_bus_free(CONFIG_CANBUS_SPI_HOST);
|
|
s_spi = NULL;
|
|
}
|
|
|
|
/* Free semaphores */
|
|
if (s_int_sem) { vSemaphoreDelete(s_int_sem); s_int_sem = NULL; }
|
|
if (s_tx_mutex) { vSemaphoreDelete(s_tx_mutex); s_tx_mutex = NULL; }
|
|
|
|
ESP_LOGI(TAG, "Deinitialized");
|
|
}
|
|
|
|
bool can_driver_is_running(void)
|
|
{
|
|
return s_running;
|
|
}
|
|
|
|
/* ============================================================
|
|
* Public API — TX / RX
|
|
* ============================================================ */
|
|
|
|
bool can_driver_send(const can_frame_t *frame)
|
|
{
|
|
if (!s_running || !s_spi) return false;
|
|
|
|
xSemaphoreTake(s_tx_mutex, portMAX_DELAY);
|
|
|
|
/* Try to load into TX buffer, with retries for busy buffer */
|
|
bool ok = false;
|
|
for (int i = 0; i < 10; i++) {
|
|
if (mcp_write_tx_buffer(frame)) {
|
|
ok = true;
|
|
break;
|
|
}
|
|
vTaskDelay(pdMS_TO_TICKS(1));
|
|
}
|
|
|
|
if (ok) {
|
|
/* Wait for TX complete (TX0IF) or timeout */
|
|
for (int i = 0; i < 100; i++) {
|
|
uint8_t intf = mcp_read_reg(MCP_CANINTF);
|
|
if (intf & MCP_TX0IF) {
|
|
mcp_modify_reg(MCP_CANINTF, MCP_TX0IF, 0x00);
|
|
s_tx_count++;
|
|
break;
|
|
}
|
|
vTaskDelay(pdMS_TO_TICKS(1));
|
|
}
|
|
}
|
|
|
|
xSemaphoreGive(s_tx_mutex);
|
|
return ok;
|
|
}
|
|
|
|
void can_driver_set_rx_callback(can_rx_callback_t cb, void *ctx)
|
|
{
|
|
s_rx_cb = cb;
|
|
s_rx_ctx = ctx;
|
|
}
|
|
|
|
void can_driver_get_rx_callback(can_rx_callback_t *cb, void **ctx)
|
|
{
|
|
if (cb) *cb = s_rx_cb;
|
|
if (ctx) *ctx = s_rx_ctx;
|
|
}
|
|
|
|
/* ============================================================
|
|
* Public API — Hardware Filters
|
|
* ============================================================ */
|
|
|
|
/* Filter register base addresses (SIDH of each filter) */
|
|
static const uint8_t s_filter_addrs[6] = {
|
|
MCP_RXF0SIDH, MCP_RXF1SIDH, MCP_RXF2SIDH,
|
|
MCP_RXF3SIDH, MCP_RXF4SIDH, MCP_RXF5SIDH,
|
|
};
|
|
|
|
static const uint8_t s_mask_addrs[2] = {
|
|
MCP_RXM0SIDH, MCP_RXM1SIDH,
|
|
};
|
|
|
|
/* Write ID to filter/mask register set (4 bytes: SIDH, SIDL, EID8, EID0) */
|
|
static void write_id_regs(uint8_t base_addr, uint32_t id, bool extended)
|
|
{
|
|
uint8_t sidh, sidl, eid8, eid0;
|
|
|
|
if (extended) {
|
|
sidh = (uint8_t)(id >> 21);
|
|
sidl = (uint8_t)((id >> 13) & 0xE0) | 0x08 | (uint8_t)((id >> 16) & 0x03);
|
|
eid8 = (uint8_t)(id >> 8);
|
|
eid0 = (uint8_t)(id);
|
|
} else {
|
|
sidh = (uint8_t)(id >> 3);
|
|
sidl = (uint8_t)((id & 0x07) << 5);
|
|
eid8 = 0;
|
|
eid0 = 0;
|
|
}
|
|
|
|
mcp_write_reg(base_addr, sidh);
|
|
mcp_write_reg(base_addr + 1, sidl);
|
|
mcp_write_reg(base_addr + 2, eid8);
|
|
mcp_write_reg(base_addr + 3, eid0);
|
|
}
|
|
|
|
bool can_driver_set_filter(int idx, uint32_t id, bool extended)
|
|
{
|
|
if (!s_spi || idx < 0 || idx > 5) return false;
|
|
|
|
/* Filters can only be set in CONFIG mode */
|
|
bool was_running = s_running;
|
|
if (was_running) can_driver_stop();
|
|
|
|
mcp_set_mode(MCP_MODE_CONFIG);
|
|
write_id_regs(s_filter_addrs[idx], id, extended);
|
|
|
|
/* Enable filtering on the relevant RX buffer */
|
|
if (idx < 2) {
|
|
mcp_write_reg(MCP_RXB0CTRL, 0x04); /* BUKT=1, RXM=00 (use filter) */
|
|
} else {
|
|
mcp_write_reg(MCP_RXB1CTRL, 0x00); /* RXM=00 (use filter) */
|
|
}
|
|
|
|
if (was_running) can_driver_start(CAN_MODE_NORMAL);
|
|
return true;
|
|
}
|
|
|
|
bool can_driver_set_mask(int idx, uint32_t mask, bool extended)
|
|
{
|
|
if (!s_spi || idx < 0 || idx > 1) return false;
|
|
|
|
bool was_running = s_running;
|
|
if (was_running) can_driver_stop();
|
|
|
|
mcp_set_mode(MCP_MODE_CONFIG);
|
|
write_id_regs(s_mask_addrs[idx], mask, extended);
|
|
|
|
if (was_running) can_driver_start(CAN_MODE_NORMAL);
|
|
return true;
|
|
}
|
|
|
|
void can_driver_clear_filters(void)
|
|
{
|
|
if (!s_spi) return;
|
|
|
|
bool was_running = s_running;
|
|
if (was_running) can_driver_stop();
|
|
|
|
mcp_set_mode(MCP_MODE_CONFIG);
|
|
|
|
/* Set masks to 0 (match anything) */
|
|
for (int i = 0; i < 2; i++) {
|
|
write_id_regs(s_mask_addrs[i], 0, false);
|
|
}
|
|
|
|
/* RXM=11 → turn off mask/filter, receive all */
|
|
mcp_write_reg(MCP_RXB0CTRL, 0x64);
|
|
mcp_write_reg(MCP_RXB1CTRL, 0x60);
|
|
|
|
if (was_running) can_driver_start(CAN_MODE_NORMAL);
|
|
}
|
|
|
|
/* ============================================================
|
|
* Public API — Status
|
|
* ============================================================ */
|
|
|
|
void can_driver_get_status(can_status_t *out)
|
|
{
|
|
memset(out, 0, sizeof(*out));
|
|
|
|
out->rx_count = s_rx_count;
|
|
out->tx_count = s_tx_count;
|
|
out->bus_errors = s_bus_errors;
|
|
out->rx_overflow = s_rx_overflow;
|
|
out->bus_off = s_bus_off;
|
|
|
|
if (s_spi) {
|
|
out->tx_errors = mcp_read_reg(MCP_TEC);
|
|
out->rx_errors = mcp_read_reg(MCP_REC);
|
|
out->error_passive = (out->tx_errors > 127) || (out->rx_errors > 127);
|
|
}
|
|
|
|
if (!s_spi) out->state = "not_initialized";
|
|
else if (!s_running) out->state = "stopped";
|
|
else if (out->bus_off) out->state = "bus_off";
|
|
else if (out->error_passive) out->state = "error_passive";
|
|
else out->state = "running";
|
|
}
|
|
|
|
/* ============================================================
|
|
* Public API — Replay
|
|
* ============================================================ */
|
|
|
|
bool can_driver_replay(const can_frame_t *frames, int count, int speed_pct)
|
|
{
|
|
if (!s_running || !frames || count <= 0) return false;
|
|
|
|
ESP_LOGI(TAG, "Replaying %d frames at %d%% speed", count, speed_pct);
|
|
|
|
int64_t base_ts = frames[0].timestamp_us;
|
|
|
|
for (int i = 0; i < count && s_running; i++) {
|
|
/* Wait for inter-frame delay */
|
|
if (i > 0 && speed_pct > 0) {
|
|
int64_t delta_us = frames[i].timestamp_us - frames[i - 1].timestamp_us;
|
|
if (delta_us > 0) {
|
|
int64_t wait_us = (delta_us * 100) / speed_pct;
|
|
if (wait_us > 1000) {
|
|
vTaskDelay(pdMS_TO_TICKS(wait_us / 1000));
|
|
}
|
|
}
|
|
}
|
|
|
|
can_frame_t tx = frames[i];
|
|
if (!can_driver_send(&tx)) {
|
|
ESP_LOGW(TAG, "Replay: send failed at frame %d", i);
|
|
}
|
|
}
|
|
|
|
ESP_LOGI(TAG, "Replay complete (%d frames)", count);
|
|
return true;
|
|
}
|
|
|
|
#endif /* CONFIG_MODULE_CANBUS */
|